A programmable logic device (PLD) is an integrated circuit (IC) that is designed to be user-programmable so that users may implement logic designs of their choices. One type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to that used in a Programmable Logic Array (PLA) or a Programmable Array Logic (PAL) device. In some CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration sequence.
Another type of PLD is a field programmable gate array (FPGA). In a typical FPGA, an array of configurable logic blocks (CLBs) is coupled to programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a hierarchy of programmable routing resources. These CLBs, IOBs, and programmable routing resources are customized by loading a configuration bitstream, typically from off-chip memory, into configuration memory cells of the FPGA. For both of these types of programmable logic devices, the functionality of the device is controlled by configuration data bits of a configuration bitstream provided to the device for that purpose. The configuration data bits may be stored in volatile memory (e.g., static memory or SRAM cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
PLDs also have different “modes” depending on the operations being performed on them. A specific protocol allows a programmable logic device to enter into the appropriate mode. Typical PLDs have internal blocks of configuration memory which specify how each of the programmable cells will emulate the user's logic. During a “program” mode, a configuration bitstream is provided to non-volatile memory, such as a read-only memory (ROM) (e.g., a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable PROM (EEPROM)) either external or internal to the programmable logic device. Each address is typically accessed by specifying its row and column addresses. During system power up of a “startup” mode, the configuration bits are successively loaded from the non-volatile memory into static random access memory (SRAM) configuration latches of a configuration logic block. At the end of this start-up phase, the PLD is now specialized to the user's design, and the PLD enters into “user” mode as part of its normal operation. Once in “user” mode, some resources of the PLD such as logic blocks, routing resources, block RAMs, distributed RAM and I/O pins are made available to the user.
However, the internal configuration memory cells of conventional devices having programmable logic are not made available to end-users. That is, conventional devices do not provide direct access to these internal configuration memory cells of the device during a user mode. In some applications where a programmable logic device has no user-available RAM, a separate memory chip is used for scratchpad memory, which is a temporary memory for storing data generated during a user mode of operation. For example, while FPGAs typically have on-chip block RAM or distributed RAM, conventional CPLDs typically do not have these resources, and circuit designers instead rely on RAM external to the CPLD.
Further, circuits implemented by different customers using PLDs are usually unique. Because PLDs are not design specific and may be used with any design, the configuration memory which is loaded with configuration data will vary based upon the user's circuit design. Therefore, even if a user knows that a given circuit design will not use all of the available memory, and particularly configuration memory, there is no way of telling which configuration memory elements will not be used or will only be partially used before a circuit design is implemented in a PLD.
Accordingly, there is a need for a circuit for and method of employing memory cells of a programmable logic device which make greater use of unused memory cells.